Many years ago, my first project was related to PCIe Gen 3. Before that, I only encountered simple protocols UART, JTAG, and APB. I still remember opening the PCIe spec, which had more than thousands of pages of hieroglyphs. How was I ever to understand it?
Fast forward to the present day, many more complex protocols are emerging. In my talks with different engineers and clients, the following three keep coming up:
- PCIe
- CXL
- UCIe
I realized it was time for me to understand better what each of these is, why they are important, and what the main differences between them are.
I spent some time researching, and here is a very simple breakdown of these protocols.
Introduction
Modern computers rely on the following components working together efficiently:
- CPUs
- GPUs
- accelerators
- memories
The way these components communicate with each otheraffects overall system performance.
PCIe, CXL, and UCIe are three key ways in which this interaction is done.
PCIe (Peripheral Component Interconnect Express)
What is PCIe?
PCIe (Peripheral Component Interconnect Express) is a key technology for high-speed communication inside computers. It’s the standard that connects components like:
- Graphics cards (GPUs)
- SSDs (NVMe storage)
- Network cards
How it works:
- PCIe provides direct, high-speed connections between the CPU and other components.
- It uses lanes to transmit data, where more lanes (like x4, x8, or x16) mean faster communication.
- It operates on a point-to-point basis, meaning each device gets a dedicated connection to the CPU.
Advantages of PCIe:
✅ High Bandwidth: PCIe 5.0 and PCIe 6.0 offer speeds of up to 64GB/s (for x16 lanes).
✅ Low Latency:Direct connections ensure fast communication.
✅ Wide Adoption: PCIe is used in nearly all modern PCs and servers.
Limitations of PCIe:
❌ Lacks Memory Sharing: PCIe is great for moving data but doesn’t allow devices to share memory efficiently with each other.
❌ Not Designed for Multi-Chip Systems: As computing moves towards chiplet-based architectures, PCIe struggles to keep up.
To summarize, PCIe is a fast highway for data movement inside a system, but as demands increase, new interconnects are needed. That’s where CXL and UCIe come in.
CXL (Compute Express Link)
What is CXL?
CXL (Compute Express Link) is an extension of PCIe designed to improve how CPUs, memory, and accelerators (like GPUs and AI chips) work together.
Think of it as PCIe with added feature—it allows devices to share memory efficiently, which is crucial for high-performance computing.
How it works:
CXL uses the same physical interface as PCIe but adds three key sub-protocols:
- CXL.io (for standard I/O operations)
- CXL.cache (for low-latency memory sharing)
- CXL.memory (for expanding memory pools).
- The main benefit is memory coherency—ensuring that all components see the same version of memory at the same time.
- This is critical for AI, cloud computing, and data centers, where different processors need fast access to shared memory.
Advantages of CXL:
✅ Memory Sharing: CPUs, GPUs, and accelerators can access the same pool of memory, reducing data duplication.
✅ Improved Efficiency:Instead of moving large chunks of data back and forth, devices can read/write directly to shared memory.
✅ Backward Compatibility: Since it builds on PCIe, existing PCIe-compatible hardware can support CXL with the right firmware.
Limitations of CXL:
❌ Not for Everything: CXL is designed for CPU-to-accelerator and memory expansion use cases, but not general-purpose component connectivity.
❌ Still Emerging: While promising, CXL adoption is still in its early stages.
CXL is a game-changer for memory-intensive applications like AI and high-performance computing, but it doesn’t solve all interconnect challenges—especially when it comes to chiplet-based designs. That’s where UCIe comes in.
UCIe (Universal Chiplet Interconnect Express)
What is UCIe?
UCIe (Universal Chiplet Interconnect Express) is a new standard designed to connect chiplets inside a single package.
Unlike PCIe and CXL, which connect separate components on a motherboard, UCIe is focused on chiplet-based architectures—where different pieces of a processor (CPU, GPU, memory) are split into smaller chiplets instead of being built as a single monolithic chip. (I wrote about chiplets here).
How it works:
- UCIe enables fast, low-power communication between chiplets in a single package.
- It supports both high-bandwidth and low-latency communication, making it ideal for modern processors that are moving away from monolithic designs.
- It allows companies to mix and match chiplets from different vendors, leading to more flexible and cost-effective designs.
- UCIe enables heterogeneous computing, allowing chiplets built on different process nodes (e.g., CPU on 3nm, memory on 7nm) to work together efficiently.
Advantages of UCIe:
✅ Optimized for Chiplets: The best solution for multi-chip processors.
✅ Lower Power Consumption:Efficient communication between chiplets minimizes energy use.
✅ Industry Standardization: Ensures chiplets from different companies can work together.
Limitations of UCIe:
❌ Not for External Devices:UCIe is only for chip-to-chip communication inside a package—it doesn’t replace PCIe or CXL for external connections.
❌ Still in Development: Like CXL, UCIe is an emerging standard that’s still evolving.
UCIe is crucial for the future of computing as chiplet-based designs become more common, allowing companies to build modular, flexible processors without needing a single, massive chip.
My favorite – table comparison:
Future Adoption and Industry Trends
- PCIe: Already widely adopted and continues to be the standard for connecting high-speed components.
- CXL: Gaining traction in AI and cloud computing, with Intel, AMD, and NVIDIA supporting it.
- UCIe: Still in early adoption but expected to dominate future chiplet-based architectures.
Which One Should You Care About?
- If you work with PCs, SSDs, or GPUs → PCIe is what connects your hardware.
- If you deal with AI, data centers, or accelerators → CXL is the future, making memory sharing seamless.
- If you’re designing next-gen processors with chiplets → UCIe is essential for enabling high-speed, low-power communication inside a single package.
Conclusion
Each of these interconnects plays a crucial role in modern computing, and as hardware continues to evolve, understanding how they work will help engineers design faster, more efficient systems.
I hope that after reading this article, you better understand the purpose of these complex protocols and the key differences between them.
Each of them is pretty complex, and if you get the opportunity to work with either of them, you will be able to learn a lot. (although it will probably be an intense job. 😊)
